Silicon-on-insulator wafers are increasingly used in the semiconductor industry. For circuits with sub-micron structures, SOI wafers may be used comprising an epitaxial top silicon layer on the insulator. This leads to a nearly default-free surface.
Semiconductor-on-insulator wafers are used by digital applications, where they have significantly improved performance over the conventional (bulk) material. It is possible to produce low-voltage and low-power devices with reduced parasitic capacitances. Thus switching times are reduced. A good decoupling between different components is possible because of the insulating oxide layer.
Semiconductor-on-insulator wafers are also used for forming combined digital and analog circuits, as well in high speed applications as in power supply applications.
A disadvantage of the presence of the buried oxide of the SOI wafer is the high cost to put the support wafer underneath the buried oxide on a defined potential. This is typically achieved by downbonding on the package. For precision applications it is necessary to have the support wafer on a defined potential (usually the most negative) in order to avoid capacitance fluctuations between the support wafer and transistor bodies.
It is generally cheaper to put the support wafer on a defined potential by providing the electrical contact by etching a cavity like a hole or a trench through the top silicon layer and the buried oxide layer. This cavity is then filled by polycrystalline silicon. But polycrystalline silicon, which is easy to handle for filling up a cavity, implies that the surface of the top silicon layer will not be monocrystalline anymore. Thus, the electrical contact creates faults in the surface of the top silicon layer. The degraded surface will lead to problems in the manufacturing of the semiconductor device on top of the top silicon layer.
Another possibility to fill up the contact cavity is to perform the usual epitaxial step for growing an active layer on the surface of the silicon top layer and filling the cavity at the same time. Although it is possible to fill the cavity during the epitaxial step, the surface of this layer will have a depression above the filled-up cavity. This depression may be of a depth of about 1 to about 2 micrometers. This depression represents a yield hazard in that it will collect particles during subsequent processing and generate defects.
It is an object of the invention to provide a method for filling up the contact cavity without degrading the surface of the top silicon layer.